Design and Implementation of Quad Core Architecture Using FPGA

The quad processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The Embedded multiprocessors face a new problem with thread safety [5]. It is caused by the shared memory, when thread safety is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique [4] and micro architectural enhancements. Therefore, designed a new Architecture called quad processor core architecture for SOC applications. This is implemented on the FPGA chip using VHDL.This architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of a Quad processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulate operations. The proposed quad processor core contains Homogeneous RISC processors [3],[7] added with pipelined processing units, multibus organization and I/o ports along with the other functional elements required to implement embedded SoC solutions. The designed Quad core performance issues like area, speed and power dissipation. Keywords— MPSoC, Quad processor, Architecture, Embedded system design, Fpga.